One of the linked papers makes the claim that the circuitry would be less complex than that needed for floats, but also includes this note:

Floats have one advantage over posits for the hardware designer: the fixed location of bits for the exponent and the fraction mean they can be decoded in parallel. With posits, there is a little serialization in having to determine the regime bits before the other bits can be decoded. There is a simple workaround for this in a processor design, similar to a trick used to speed the exception handling of floats: Some extra register bits can be attached to each value to save the need for extracting size information when decoding instructions.

The proposed system also lacks NaN and separate positive/negative infinities, so it wouldn’t be a drop-in replacement.